Major refactor of codebase

include/arch/amd64/hal/apic.h

@@ -0,0 +1,4 @@
+
+void apic_init(void);
+void ap_apic_init();
+void apic_sleep(int ms);

include/arch/amd64/hal/gdt.h

@@ -0,0 +1,17 @@
+#include <stdint.h>
+
+typedef struct gdt_descriptor {
+    uint16_t limit_low;
+    uint16_t base_low;
+	uint8_t base_middle;
+	uint8_t access;
+	uint8_t granularity;
+	uint8_t base_high;
+} __attribute((packed)) gdt_descriptor;
+
+typedef struct gdt_register {
+    uint16_t limit;
+    uint64_t base_address;
+} __attribute((packed)) gdt_register;
+
+void set_gdt(void);

include/arch/amd64/hal/idt.h

@@ -0,0 +1,42 @@
+#include <error.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+typedef struct idt_descriptor {
+    uint16_t offset_low;
+    uint16_t segment_sel;
+    uint8_t ist;
+    uint8_t attributes;
+    uint16_t offset_high;
+    uint32_t offset_higher;
+    uint32_t reserved;
+} __attribute((packed))idt_descriptor;
+
+typedef struct idt_register {
+    uint16_t limit;
+    uint64_t base_address;
+} __attribute((packed)) idt_register;
+
+typedef struct interrupt_frame {
+	uint64_t r15, r14, r13, r12, r11, r10, r9, r8, rdi, rsi, rbp, rdx, rcx, rbx, rax;
+    uint64_t int_no, err;
+	uint64_t rip, cs, rflags, rsp, ss;
+} __attribute((packed)) interrupt_frame;
+
+typedef struct stack_frame {
+    struct stack_frame *rbp;
+    uint64_t rip;
+}__attribute((packed)) stack_frame;
+
+typedef struct irq_t {
+    void *base;
+    bool in_use;
+}irq_t;
+
+void set_idt_descriptor(uint8_t vector, void *base, uint8_t flags);
+
+kstatus register_irq_vector(uint8_t vector, void *base, uint8_t flags);
+
+int register_irq(void *base, uint8_t flags);
+
+void set_idt(void);

include/arch/amd64/hal/ioapic.h

@@ -0,0 +1,13 @@
+#include "error.h"
+#include <stdint.h>
+void ioapic_init(void);
+void write_redir_entry(uint8_t reg, uint64_t data);
+kstatus set_redir_entry(uint8_t pin, uint8_t vector, uint8_t delivery, uint8_t trigger, uint8_t destination_field, uint8_t destination_mode);
+
+#define IOREGSEL    0x0
+#define IOWIN       0x10
+
+#define IOAPICID    0x0
+#define IOAPICVER   0x1
+#define IOAPICARB   0x2
+#define IOREDTBL(x) (0x10 + (x * 2)) // 0-23 registers

include/arch/amd64/hal/smp.h

@@ -0,0 +1,26 @@
+#include <stdbool.h>
+#include <stdint.h>
+#include <scheduler/sched.h>
+
+#pragma once
+
+#define GSBASE 0xC0000101
+#define KERNELGSBASE 0xC0000102
+
+typedef struct cpu_state {
+    uint32_t lapic_id;
+    uint64_t lapic_timer_ticks;
+    struct thread *head;
+    struct thread *base;
+    struct thread *current_process;
+    uint16_t process_count;
+    struct context *scheduler_context;
+    uint64_t *scheduler_stack;
+    bool scheduler_initialized;
+}cpu_state;
+
+void smp_init();
+cpu_state *get_cpu_struct();
+uint64_t get_cpu_count();
+bool get_cpu_struct_initialized();
+

include/arch/amd64/hal/timer.h

@@ -0,0 +1,11 @@
+#include <stdint.h>
+
+enum USABLE_TIMERS {
+    HPET = 0,
+    PMT,
+    PIT,
+};
+
+void timer_init(void);
+void apic_timer_handler(void);
+void sleep(int ms);

include/arch/amd64/hal/tsc.h

@@ -0,0 +1,6 @@
+#include "error.h"
+#include <stdint.h>
+
+kstatus tsc_init();
+
+uint64_t tsc_get_timestamp();