Major refactor of codebase

include/arch/amd64/hal/apic.h

@@ -0,0 +1,4 @@
+
+void apic_init(void);
+void ap_apic_init();
+void apic_sleep(int ms);

include/arch/amd64/hal/gdt.h

@@ -0,0 +1,17 @@
+#include <stdint.h>
+
+typedef struct gdt_descriptor {
+    uint16_t limit_low;
+    uint16_t base_low;
+	uint8_t base_middle;
+	uint8_t access;
+	uint8_t granularity;
+	uint8_t base_high;
+} __attribute((packed)) gdt_descriptor;
+
+typedef struct gdt_register {
+    uint16_t limit;
+    uint64_t base_address;
+} __attribute((packed)) gdt_register;
+
+void set_gdt(void);

include/arch/amd64/hal/idt.h

@@ -0,0 +1,42 @@
+#include <error.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+typedef struct idt_descriptor {
+    uint16_t offset_low;
+    uint16_t segment_sel;
+    uint8_t ist;
+    uint8_t attributes;
+    uint16_t offset_high;
+    uint32_t offset_higher;
+    uint32_t reserved;
+} __attribute((packed))idt_descriptor;
+
+typedef struct idt_register {
+    uint16_t limit;
+    uint64_t base_address;
+} __attribute((packed)) idt_register;
+
+typedef struct interrupt_frame {
+	uint64_t r15, r14, r13, r12, r11, r10, r9, r8, rdi, rsi, rbp, rdx, rcx, rbx, rax;
+    uint64_t int_no, err;
+	uint64_t rip, cs, rflags, rsp, ss;
+} __attribute((packed)) interrupt_frame;
+
+typedef struct stack_frame {
+    struct stack_frame *rbp;
+    uint64_t rip;
+}__attribute((packed)) stack_frame;
+
+typedef struct irq_t {
+    void *base;
+    bool in_use;
+}irq_t;
+
+void set_idt_descriptor(uint8_t vector, void *base, uint8_t flags);
+
+kstatus register_irq_vector(uint8_t vector, void *base, uint8_t flags);
+
+int register_irq(void *base, uint8_t flags);
+
+void set_idt(void);

include/arch/amd64/hal/ioapic.h

@@ -0,0 +1,13 @@
+#include "error.h"
+#include <stdint.h>
+void ioapic_init(void);
+void write_redir_entry(uint8_t reg, uint64_t data);
+kstatus set_redir_entry(uint8_t pin, uint8_t vector, uint8_t delivery, uint8_t trigger, uint8_t destination_field, uint8_t destination_mode);
+
+#define IOREGSEL    0x0
+#define IOWIN       0x10
+
+#define IOAPICID    0x0
+#define IOAPICVER   0x1
+#define IOAPICARB   0x2
+#define IOREDTBL(x) (0x10 + (x * 2)) // 0-23 registers

include/arch/amd64/hal/smp.h

@@ -0,0 +1,26 @@
+#include <stdbool.h>
+#include <stdint.h>
+#include <scheduler/sched.h>
+
+#pragma once
+
+#define GSBASE 0xC0000101
+#define KERNELGSBASE 0xC0000102
+
+typedef struct cpu_state {
+    uint32_t lapic_id;
+    uint64_t lapic_timer_ticks;
+    struct thread *head;
+    struct thread *base;
+    struct thread *current_process;
+    uint16_t process_count;
+    struct context *scheduler_context;
+    uint64_t *scheduler_stack;
+    bool scheduler_initialized;
+}cpu_state;
+
+void smp_init();
+cpu_state *get_cpu_struct();
+uint64_t get_cpu_count();
+bool get_cpu_struct_initialized();
+

include/arch/amd64/hal/timer.h

@@ -0,0 +1,11 @@
+#include <stdint.h>
+
+enum USABLE_TIMERS {
+    HPET = 0,
+    PMT,
+    PIT,
+};
+
+void timer_init(void);
+void apic_timer_handler(void);
+void sleep(int ms);

include/arch/amd64/hal/tsc.h

@@ -0,0 +1,6 @@
+#include "error.h"
+#include <stdint.h>
+
+kstatus tsc_init();
+
+uint64_t tsc_get_timestamp();

include/assert.h

@@ -0,0 +1,10 @@
+#pragma once
+
+// Thanks to Managarm: 
+// https://github.com/managarm/managarm/blob/master/kernel/klibc/assert.h
+
+void __assert_fail(const char *assertion, const char *file, unsigned int line,
+		const char *function);
+
+#define assert(assertion) ((void)((assertion) \
+		|| (__assert_fail(#assertion, __FILE__, __LINE__, __func__), 0)))

include/drivers/ahci.h

@@ -0,0 +1 @@
+void ahci_init();

include/drivers/pmt.h

@@ -0,0 +1,3 @@
+#include <stdint.h>
+int pmt_init();
+void pmt_delay(uint64_t us);

include/drivers/serial.h

@@ -0,0 +1,8 @@
+#include <stdint.h>
+
+void serial_write(uint8_t data);
+uint8_t serial_read();
+
+void serial_print(char *str);
+
+void serial_init();

include/error.h

@@ -0,0 +1,14 @@
+#ifndef ERROR_H
+#define ERROR_H
+
+typedef enum {
+    /* Success */
+    KERNEL_STATUS_SUCCESS,
+
+    /* General error */
+    KERNEL_STATUS_ERROR,
+} kstatus;
+
+
+
+#endif

include/io.h

@@ -0,0 +1,12 @@
+#include <stdint.h>
+
+void outb(uint16_t port, uint8_t val);
+void outw(uint16_t port, uint16_t val);
+void outl(uint16_t port, uint32_t val);
+
+uint8_t inb(uint16_t port);
+uint16_t inw(uint16_t port);
+uint32_t inl(uint16_t port);
+
+void wrmsr(uint64_t msr, uint64_t value);
+uint64_t rdmsr(uint64_t msr);

include/kmath.h

@@ -0,0 +1 @@
+#define abs(x) (x<0) ? -x : x

include/kprint.h

@@ -0,0 +1,42 @@
+#include <stdint.h>
+#include "../build/flanterm/src/flanterm.h"
+#include "../build/flanterm/src/flanterm_backends/fb.h"
+
+enum {
+    LOG_INFO = 0,
+    LOG_WARN,
+    LOG_ERROR,
+    LOG_SUCCESS,
+};
+
+void klog(const char *func, const char *msg, ...);
+
+int kprintf(const char *format_string, ...);
+
+int serial_kprintf(const char *format_string, ...);
+
+void print_char(struct flanterm_context *ft_ctx, char c);
+void print_str(struct flanterm_context *ft_ctx, char *str);
+void print_int(struct flanterm_context *ft_ctx, uint64_t i);
+void print_hex(struct flanterm_context *ft_ctx, uint64_t num);
+void print_bin(struct flanterm_context *ft_ctx, uint64_t num);
+
+void serial_print_char(char c);
+void serial_print_int(uint64_t i);
+void serial_print_hex(uint64_t num);
+void serial_print_bin(uint64_t num);
+
+void kernel_framebuffer_print(char *buffer, size_t n);
+void kernel_serial_print(char *buffer, size_t n);
+
+char toupper(char c);
+char dtoc(int digit);
+
+
+#define ANSI_COLOR_RED     "\x1b[31m"
+#define ANSI_COLOR_GREEN   "\x1b[32m"
+#define ANSI_COLOR_YELLOW  "\x1b[33m"
+#define ANSI_COLOR_BLUE    "\x1b[34m"
+#define ANSI_COLOR_MAGENTA "\x1b[35m"
+#define ANSI_COLOR_CYAN    "\x1b[36m"
+#define ANSI_COLOR_RESET   "\x1b[0m"

include/limine.h

@@ -0,0 +1,621 @@
+/* BSD Zero Clause License */
+
+/* Copyright (C) 2022-2024 mintsuki and contributors.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef LIMINE_H
+#define LIMINE_H 1
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/* Misc */
+
+#ifdef LIMINE_NO_POINTERS
+#  define LIMINE_PTR(TYPE) uint64_t
+#else
+#  define LIMINE_PTR(TYPE) TYPE
+#endif
+
+#ifdef __GNUC__
+#  define LIMINE_DEPRECATED __attribute__((__deprecated__))
+#  define LIMINE_DEPRECATED_IGNORE_START \
+    _Pragma("GCC diagnostic push") \
+    _Pragma("GCC diagnostic ignored \"-Wdeprecated-declarations\"")
+#  define LIMINE_DEPRECATED_IGNORE_END \
+    _Pragma("GCC diagnostic pop")
+#else
+#  define LIMINE_DEPRECATED
+#  define LIMINE_DEPRECATED_IGNORE_START
+#  define LIMINE_DEPRECATED_IGNORE_END
+#endif
+
+#define LIMINE_REQUESTS_START_MARKER \
+    uint64_t limine_requests_start_marker[4] = { 0xf6b8f4b39de7d1ae, 0xfab91a6940fcb9cf, \
+                                                 0x785c6ed015d3e316, 0x181e920a7852b9d9 };
+#define LIMINE_REQUESTS_END_MARKER \
+    uint64_t limine_requests_end_marker[2] = { 0xadc0e0531bb10d03, 0x9572709f31764c62 };
+
+#define LIMINE_REQUESTS_DELIMITER LIMINE_REQUESTS_END_MARKER
+
+#define LIMINE_BASE_REVISION(N) \
+    uint64_t limine_base_revision[3] = { 0xf9562b2d5c95a6c8, 0x6a7b384944536bdc, (N) };
+
+#define LIMINE_BASE_REVISION_SUPPORTED (limine_base_revision[2] == 0)
+
+#define LIMINE_COMMON_MAGIC 0xc7b1dd30df4c8b88, 0x0a82e883a194f07b
+
+struct limine_uuid {
+    uint32_t a;
+    uint16_t b;
+    uint16_t c;
+    uint8_t d[8];
+};
+
+#define LIMINE_MEDIA_TYPE_GENERIC 0
+#define LIMINE_MEDIA_TYPE_OPTICAL 1
+#define LIMINE_MEDIA_TYPE_TFTP 2
+
+struct limine_file {
+    uint64_t revision;
+    LIMINE_PTR(void *) address;
+    uint64_t size;
+    LIMINE_PTR(char *) path;
+    LIMINE_PTR(char *) cmdline;
+    uint32_t media_type;
+    uint32_t unused;
+    uint32_t tftp_ip;
+    uint32_t tftp_port;
+    uint32_t partition_index;
+    uint32_t mbr_disk_id;
+    struct limine_uuid gpt_disk_uuid;
+    struct limine_uuid gpt_part_uuid;
+    struct limine_uuid part_uuid;
+};
+
+/* Boot info */
+
+#define LIMINE_BOOTLOADER_INFO_REQUEST { LIMINE_COMMON_MAGIC, 0xf55038d8e2a1202f, 0x279426fcf5f59740 }
+
+struct limine_bootloader_info_response {
+    uint64_t revision;
+    LIMINE_PTR(char *) name;
+    LIMINE_PTR(char *) version;
+};
+
+struct limine_bootloader_info_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_bootloader_info_response *) response;
+};
+
+/* Firmware type */
+
+#define LIMINE_FIRMWARE_TYPE_REQUEST { LIMINE_COMMON_MAGIC, 0x8c2f75d90bef28a8, 0x7045a4688eac00c3 }
+
+#define LIMINE_FIRMWARE_TYPE_X86BIOS 0
+#define LIMINE_FIRMWARE_TYPE_UEFI32 1
+#define LIMINE_FIRMWARE_TYPE_UEFI64 2
+
+struct limine_firmware_type_response {
+    uint64_t revision;
+    uint64_t firmware_type;
+};
+
+struct limine_firmware_type_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_firmware_type_response *) response;
+};
+
+/* Stack size */
+
+#define LIMINE_STACK_SIZE_REQUEST { LIMINE_COMMON_MAGIC, 0x224ef0460a8e8926, 0xe1cb0fc25f46ea3d }
+
+struct limine_stack_size_response {
+    uint64_t revision;
+};
+
+struct limine_stack_size_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_stack_size_response *) response;
+    uint64_t stack_size;
+};
+
+/* HHDM */
+
+#define LIMINE_HHDM_REQUEST { LIMINE_COMMON_MAGIC, 0x48dcf1cb8ad2b852, 0x63984e959a98244b }
+
+struct limine_hhdm_response {
+    uint64_t revision;
+    uint64_t offset;
+};
+
+struct limine_hhdm_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_hhdm_response *) response;
+};
+
+/* Framebuffer */
+
+#define LIMINE_FRAMEBUFFER_REQUEST { LIMINE_COMMON_MAGIC, 0x9d5827dcd881dd75, 0xa3148604f6fab11b }
+
+#define LIMINE_FRAMEBUFFER_RGB 1
+
+struct limine_video_mode {
+    uint64_t pitch;
+    uint64_t width;
+    uint64_t height;
+    uint16_t bpp;
+    uint8_t memory_model;
+    uint8_t red_mask_size;
+    uint8_t red_mask_shift;
+    uint8_t green_mask_size;
+    uint8_t green_mask_shift;
+    uint8_t blue_mask_size;
+    uint8_t blue_mask_shift;
+};
+
+struct limine_framebuffer {
+    LIMINE_PTR(void *) address;
+    uint64_t width;
+    uint64_t height;
+    uint64_t pitch;
+    uint16_t bpp;
+    uint8_t memory_model;
+    uint8_t red_mask_size;
+    uint8_t red_mask_shift;
+    uint8_t green_mask_size;
+    uint8_t green_mask_shift;
+    uint8_t blue_mask_size;
+    uint8_t blue_mask_shift;
+    uint8_t unused[7];
+    uint64_t edid_size;
+    LIMINE_PTR(void *) edid;
+    /* Response revision 1 */
+    uint64_t mode_count;
+    LIMINE_PTR(struct limine_video_mode **) modes;
+};
+
+struct limine_framebuffer_response {
+    uint64_t revision;
+    uint64_t framebuffer_count;
+    LIMINE_PTR(struct limine_framebuffer **) framebuffers;
+};
+
+struct limine_framebuffer_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_framebuffer_response *) response;
+};
+
+/* Terminal */
+
+#define LIMINE_TERMINAL_REQUEST { LIMINE_COMMON_MAGIC, 0xc8ac59310c2b0844, 0xa68d0c7265d38878 }
+
+#define LIMINE_TERMINAL_CB_DEC 10
+#define LIMINE_TERMINAL_CB_BELL 20
+#define LIMINE_TERMINAL_CB_PRIVATE_ID 30
+#define LIMINE_TERMINAL_CB_STATUS_REPORT 40
+#define LIMINE_TERMINAL_CB_POS_REPORT 50
+#define LIMINE_TERMINAL_CB_KBD_LEDS 60
+#define LIMINE_TERMINAL_CB_MODE 70
+#define LIMINE_TERMINAL_CB_LINUX 80
+
+#define LIMINE_TERMINAL_CTX_SIZE ((uint64_t)(-1))
+#define LIMINE_TERMINAL_CTX_SAVE ((uint64_t)(-2))
+#define LIMINE_TERMINAL_CTX_RESTORE ((uint64_t)(-3))
+#define LIMINE_TERMINAL_FULL_REFRESH ((uint64_t)(-4))
+
+/* Response revision 1 */
+#define LIMINE_TERMINAL_OOB_OUTPUT_GET ((uint64_t)(-10))
+#define LIMINE_TERMINAL_OOB_OUTPUT_SET ((uint64_t)(-11))
+
+#define LIMINE_TERMINAL_OOB_OUTPUT_OCRNL (1 << 0)
+#define LIMINE_TERMINAL_OOB_OUTPUT_OFDEL (1 << 1)
+#define LIMINE_TERMINAL_OOB_OUTPUT_OFILL (1 << 2)
+#define LIMINE_TERMINAL_OOB_OUTPUT_OLCUC (1 << 3)
+#define LIMINE_TERMINAL_OOB_OUTPUT_ONLCR (1 << 4)
+#define LIMINE_TERMINAL_OOB_OUTPUT_ONLRET (1 << 5)
+#define LIMINE_TERMINAL_OOB_OUTPUT_ONOCR (1 << 6)
+#define LIMINE_TERMINAL_OOB_OUTPUT_OPOST (1 << 7)
+
+LIMINE_DEPRECATED_IGNORE_START
+
+struct LIMINE_DEPRECATED limine_terminal;
+
+typedef void (*limine_terminal_write)(struct limine_terminal *, const char *, uint64_t);
+typedef void (*limine_terminal_callback)(struct limine_terminal *, uint64_t, uint64_t, uint64_t, uint64_t);
+
+struct LIMINE_DEPRECATED limine_terminal {
+    uint64_t columns;
+    uint64_t rows;
+    LIMINE_PTR(struct limine_framebuffer *) framebuffer;
+};
+
+struct LIMINE_DEPRECATED limine_terminal_response {
+    uint64_t revision;
+    uint64_t terminal_count;
+    LIMINE_PTR(struct limine_terminal **) terminals;
+    LIMINE_PTR(limine_terminal_write) write;
+};
+
+struct LIMINE_DEPRECATED limine_terminal_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_terminal_response *) response;
+    LIMINE_PTR(limine_terminal_callback) callback;
+};
+
+LIMINE_DEPRECATED_IGNORE_END
+
+/* Paging mode */
+
+#define LIMINE_PAGING_MODE_REQUEST { LIMINE_COMMON_MAGIC, 0x95c1a0edab0944cb, 0xa4e5cb3842f7488a }
+
+#if defined (__x86_64__) || defined (__i386__)
+#define LIMINE_PAGING_MODE_X86_64_4LVL 0
+#define LIMINE_PAGING_MODE_X86_64_5LVL 1
+#define LIMINE_PAGING_MODE_MIN LIMINE_PAGING_MODE_X86_64_4LVL
+#define LIMINE_PAGING_MODE_DEFAULT LIMINE_PAGING_MODE_X86_64_4LVL
+#elif defined (__aarch64__)
+#define LIMINE_PAGING_MODE_AARCH64_4LVL 0
+#define LIMINE_PAGING_MODE_AARCH64_5LVL 1
+#define LIMINE_PAGING_MODE_MIN LIMINE_PAGING_MODE_AARCH64_4LVL
+#define LIMINE_PAGING_MODE_DEFAULT LIMINE_PAGING_MODE_AARCH64_4LVL
+#elif defined (__riscv) && (__riscv_xlen == 64)
+#define LIMINE_PAGING_MODE_RISCV_SV39 0
+#define LIMINE_PAGING_MODE_RISCV_SV48 1
+#define LIMINE_PAGING_MODE_RISCV_SV57 2
+#define LIMINE_PAGING_MODE_MIN LIMINE_PAGING_MODE_RISCV_SV39
+#define LIMINE_PAGING_MODE_DEFAULT LIMINE_PAGING_MODE_RISCV_SV48
+#elif defined (__loongarch__) && (__loongarch_grlen == 64)
+#define LIMINE_PAGING_MODE_LOONGARCH64_4LVL 0
+#define LIMINE_PAGING_MODE_MIN LIMINE_PAGING_MODE_LOONGARCH64_4LVL
+#define LIMINE_PAGING_MODE_DEFAULT LIMINE_PAGING_MODE_LOONGARCH64_4LVL
+#else
+#error Unknown architecture
+#endif
+
+struct limine_paging_mode_response {
+    uint64_t revision;
+    uint64_t mode;
+};
+
+struct limine_paging_mode_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_paging_mode_response *) response;
+    uint64_t mode;
+    uint64_t max_mode;
+    uint64_t min_mode;
+};
+
+/* 5-level paging */
+
+#define LIMINE_5_LEVEL_PAGING_REQUEST { LIMINE_COMMON_MAGIC, 0x94469551da9b3192, 0xebe5e86db7382888 }
+
+LIMINE_DEPRECATED_IGNORE_START
+
+struct LIMINE_DEPRECATED limine_5_level_paging_response {
+    uint64_t revision;
+};
+
+struct LIMINE_DEPRECATED limine_5_level_paging_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_5_level_paging_response *) response;
+};
+
+LIMINE_DEPRECATED_IGNORE_END
+
+/* SMP */
+
+#define LIMINE_SMP_REQUEST { LIMINE_COMMON_MAGIC, 0x95a67b819a1b857e, 0xa0b61b723b6a73e0 }
+
+struct limine_smp_info;
+
+typedef void (*limine_goto_address)(struct limine_smp_info *);
+
+#if defined (__x86_64__) || defined (__i386__)
+
+#define LIMINE_SMP_X2APIC (1 << 0)
+
+struct limine_smp_info {
+    uint32_t processor_id;
+    uint32_t lapic_id;
+    uint64_t reserved;
+    LIMINE_PTR(limine_goto_address) goto_address;
+    uint64_t extra_argument;
+};
+
+struct limine_smp_response {
+    uint64_t revision;
+    uint32_t flags;
+    uint32_t bsp_lapic_id;
+    uint64_t cpu_count;
+    LIMINE_PTR(struct limine_smp_info **) cpus;
+};
+
+#elif defined (__aarch64__)
+
+struct limine_smp_info {
+    uint32_t processor_id;
+    uint32_t reserved1;
+    uint64_t mpidr;
+    uint64_t reserved;
+    LIMINE_PTR(limine_goto_address) goto_address;
+    uint64_t extra_argument;
+};
+
+struct limine_smp_response {
+    uint64_t revision;
+    uint64_t flags;
+    uint64_t bsp_mpidr;
+    uint64_t cpu_count;
+    LIMINE_PTR(struct limine_smp_info **) cpus;
+};
+
+#elif defined (__riscv) && (__riscv_xlen == 64)
+
+struct limine_smp_info {
+    uint64_t processor_id;
+    uint64_t hartid;
+    uint64_t reserved;
+    LIMINE_PTR(limine_goto_address) goto_address;
+    uint64_t extra_argument;
+};
+
+struct limine_smp_response {
+    uint64_t revision;
+    uint64_t flags;
+    uint64_t bsp_hartid;
+    uint64_t cpu_count;
+    LIMINE_PTR(struct limine_smp_info **) cpus;
+};
+
+#elif defined (__loongarch__) && (__loongarch_grlen == 64)
+
+struct limine_smp_info {
+    uint64_t reserved;
+};
+
+struct limine_smp_response {
+    uint64_t cpu_count;
+    LIMINE_PTR(struct limine_smp_info **) cpus;
+};
+
+#else
+#error Unknown architecture
+#endif
+
+struct limine_smp_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_smp_response *) response;
+    uint64_t flags;
+};
+
+/* Memory map */
+
+#define LIMINE_MEMMAP_REQUEST { LIMINE_COMMON_MAGIC, 0x67cf3d9d378a806f, 0xe304acdfc50c3c62 }
+
+#define LIMINE_MEMMAP_USABLE                 0
+#define LIMINE_MEMMAP_RESERVED               1
+#define LIMINE_MEMMAP_ACPI_RECLAIMABLE       2
+#define LIMINE_MEMMAP_ACPI_NVS               3
+#define LIMINE_MEMMAP_BAD_MEMORY             4
+#define LIMINE_MEMMAP_BOOTLOADER_RECLAIMABLE 5
+#define LIMINE_MEMMAP_KERNEL_AND_MODULES     6
+#define LIMINE_MEMMAP_FRAMEBUFFER            7
+
+struct limine_memmap_entry {
+    uint64_t base;
+    uint64_t length;
+    uint64_t type;
+};
+
+struct limine_memmap_response {
+    uint64_t revision;
+    uint64_t entry_count;
+    LIMINE_PTR(struct limine_memmap_entry **) entries;
+};
+
+struct limine_memmap_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_memmap_response *) response;
+};
+
+/* Entry point */
+
+#define LIMINE_ENTRY_POINT_REQUEST { LIMINE_COMMON_MAGIC, 0x13d86c035a1cd3e1, 0x2b0caa89d8f3026a }
+
+typedef void (*limine_entry_point)(void);
+
+struct limine_entry_point_response {
+    uint64_t revision;
+};
+
+struct limine_entry_point_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_entry_point_response *) response;
+    LIMINE_PTR(limine_entry_point) entry;
+};
+
+/* Kernel File */
+
+#define LIMINE_KERNEL_FILE_REQUEST { LIMINE_COMMON_MAGIC, 0xad97e90e83f1ed67, 0x31eb5d1c5ff23b69 }
+
+struct limine_kernel_file_response {
+    uint64_t revision;
+    LIMINE_PTR(struct limine_file *) kernel_file;
+};
+
+struct limine_kernel_file_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_kernel_file_response *) response;
+};
+
+/* Module */
+
+#define LIMINE_MODULE_REQUEST { LIMINE_COMMON_MAGIC, 0x3e7e279702be32af, 0xca1c4f3bd1280cee }
+
+#define LIMINE_INTERNAL_MODULE_REQUIRED (1 << 0)
+#define LIMINE_INTERNAL_MODULE_COMPRESSED (1 << 1)
+
+struct limine_internal_module {
+    LIMINE_PTR(const char *) path;
+    LIMINE_PTR(const char *) cmdline;
+    uint64_t flags;
+};
+
+struct limine_module_response {
+    uint64_t revision;
+    uint64_t module_count;
+    LIMINE_PTR(struct limine_file **) modules;
+};
+
+struct limine_module_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_module_response *) response;
+
+    /* Request revision 1 */
+    uint64_t internal_module_count;
+    LIMINE_PTR(struct limine_internal_module **) internal_modules;
+};
+
+/* RSDP */
+
+#define LIMINE_RSDP_REQUEST { LIMINE_COMMON_MAGIC, 0xc5e77b6b397e7b43, 0x27637845accdcf3c }
+
+struct limine_rsdp_response {
+    uint64_t revision;
+    LIMINE_PTR(void *) address;
+};
+
+struct limine_rsdp_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_rsdp_response *) response;
+};
+
+/* SMBIOS */
+
+#define LIMINE_SMBIOS_REQUEST { LIMINE_COMMON_MAGIC, 0x9e9046f11e095391, 0xaa4a520fefbde5ee }
+
+struct limine_smbios_response {
+    uint64_t revision;
+    LIMINE_PTR(void *) entry_32;
+    LIMINE_PTR(void *) entry_64;
+};
+
+struct limine_smbios_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_smbios_response *) response;
+};
+
+/* EFI system table */
+
+#define LIMINE_EFI_SYSTEM_TABLE_REQUEST { LIMINE_COMMON_MAGIC, 0x5ceba5163eaaf6d6, 0x0a6981610cf65fcc }
+
+struct limine_efi_system_table_response {
+    uint64_t revision;
+    LIMINE_PTR(void *) address;
+};
+
+struct limine_efi_system_table_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_efi_system_table_response *) response;
+};
+
+/* EFI memory map */
+
+#define LIMINE_EFI_MEMMAP_REQUEST { LIMINE_COMMON_MAGIC, 0x7df62a431d6872d5, 0xa4fcdfb3e57306c8 }
+
+struct limine_efi_memmap_response {
+    uint64_t revision;
+    LIMINE_PTR(void *) memmap;
+    uint64_t memmap_size;
+    uint64_t desc_size;
+    uint64_t desc_version;
+};
+
+struct limine_efi_memmap_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_efi_memmap_response *) response;
+};
+
+/* Boot time */
+
+#define LIMINE_BOOT_TIME_REQUEST { LIMINE_COMMON_MAGIC, 0x502746e184c088aa, 0xfbc5ec83e6327893 }
+
+struct limine_boot_time_response {
+    uint64_t revision;
+    int64_t boot_time;
+};
+
+struct limine_boot_time_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_boot_time_response *) response;
+};
+
+/* Kernel address */
+
+#define LIMINE_KERNEL_ADDRESS_REQUEST { LIMINE_COMMON_MAGIC, 0x71ba76863cc55f63, 0xb2644a48c516a487 }
+
+struct limine_kernel_address_response {
+    uint64_t revision;
+    uint64_t physical_base;
+    uint64_t virtual_base;
+};
+
+struct limine_kernel_address_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_kernel_address_response *) response;
+};
+
+/* Device Tree Blob */
+
+#define LIMINE_DTB_REQUEST { LIMINE_COMMON_MAGIC, 0xb40ddb48fb54bac7, 0x545081493f81ffb7 }
+
+struct limine_dtb_response {
+    uint64_t revision;
+    LIMINE_PTR(void *) dtb_ptr;
+};
+
+struct limine_dtb_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_dtb_response *) response;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

include/lock.h

@@ -0,0 +1,9 @@
+#include <stdatomic.h>
+
+#ifndef SPINLOCK_H
+#define SPINLOCK_H
+
+void acquire_spinlock(atomic_flag *lock);
+void free_spinlock(atomic_flag *lock);
+
+#endif

include/mm/kmalloc.h

@@ -0,0 +1,9 @@
+#include <error.h>
+#include <stddef.h>
+#include <stdint.h>
+
+void _kmalloc_init(void);
+
+void *kmalloc(size_t size);
+void *kzalloc(size_t size);
+kstatus kfree(void *addr);

include/mm/page.h

@@ -0,0 +1,10 @@
+#include "slab.h"
+
+typedef struct page {
+    struct ma_bufctl *bufctls; // The bufctls associated with the slab stored on this page. NULL if page isn't associated with a slab
+    struct ma_slab *slab;
+}page;
+
+struct page *get_page(void *addr);
+
+void init_page_array();

include/mm/pmm.h

@@ -0,0 +1,13 @@
+#include <stdbool.h>
+#include <stdint.h>
+
+#define BLOCK_SIZE 4096
+
+typedef struct free_page_t {
+    struct free_page_t *next;
+    uint8_t _padding[4088];
+} __attribute((packed)) free_page_t;
+
+void pmm_init(void);
+uint64_t *pmm_alloc();
+void pmm_free(uint64_t *addr);

include/mm/slab.h

@@ -0,0 +1,60 @@
+#include <stdatomic.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <error.h>
+#include <stdbool.h>
+
+#pragma once
+#define KCACHE_NAME_LEN 16
+
+
+struct ma_bufctl {
+    struct ma_bufctl *next;
+    size_t *startaddr;
+};
+// ADD COLORING
+struct ma_slab {
+    struct ma_cache *cache;
+
+    struct ma_slab *next;
+    struct ma_slab *prev;
+
+    uint32_t refcount; // The amount of active (not free) objects in the slabs
+
+    atomic_flag lock;
+
+    struct ma_bufctl *free; // Linked list of free buffers in the slab. Is equal to NULL once there are no more free objects 
+};
+
+/* objrefs are used to be able to quickly find out which slab and cache a object belongs to. objrefs belonging to the same slab are kept in one page, there is no mixing. */
+struct ma_objref { 
+    struct ma_objref *next;
+    struct ma_objref *prev;
+    void *addr; // Addr of the object
+    struct ma_slab *slab; // The slab which the obj belongs to
+    struct ma_cache *kcache; // The cache which the obj belongs to
+};
+
+struct ma_cache {
+    struct ma_cache *next;    
+    struct ma_cache *prev;
+
+    uint32_t objsize; // Size of the object which the cache stores
+    uint16_t flags; // Not useful yet
+    uint32_t num; // Number of objects per slab
+    uint32_t slabsize; // How many pages does a single slab take up. Useful for objects > PAGE_SIZE
+    
+    struct ma_slab *slabs_free;
+    struct ma_slab *slabs_partial;
+    struct ma_slab *slabs_used;
+
+    atomic_flag lock;
+
+    char name[KCACHE_NAME_LEN];
+};
+
+void *ma_cache_alloc(struct ma_cache *kcache, uint32_t flags);
+kstatus ma_cache_dealloc(void *object);
+struct ma_cache *ma_cache_create(char *name, size_t size, uint32_t flags, void (*constructor)(void *, size_t), void (*destructor)(void *, size_t));
+void cache_info(struct ma_cache *cache);
+void create_base_caches();

include/mm/vmm.h

@@ -0,0 +1,25 @@
+
+#include <stdint.h>
+
+#define PTE_BIT_PRESENT     0x1                 // Present bit
+#define PTE_BIT_RW          0x2                 // Read/write bit
+#define PTE_BIT_US          0x4                 // User and Supervisor bit
+#define PTE_BIT_NX          0x4000000000000000  // Non-executable bit
+#define PTE_BIT_UNCACHABLE  (1 << 4)
+
+#define PAGE_SIZE 4096
+
+void tlb_flush(void);
+void vmm_map_page(uint64_t *page_map, uint64_t virt_address, uint64_t phys_address, uint64_t flags);
+int vmm_map_contigious_pages(uint64_t *page_map, uint64_t virt_addr, uint64_t phys_addr, uint64_t size, uint64_t flags);
+void vmm_free_page(uint64_t *page_map, uint64_t virt_addr);
+void vmm_init();
+void vmm_set_ctx(uint64_t *page_map);
+uint64_t vmm_get_phys_addr(uint64_t *page_map, uint64_t virt_addr);
+uint64_t kget_phys_addr(uint64_t *virt_addr);
+void *va_alloc_contigious_pages(uint64_t size);
+void kmap_pages(void *phys_addr, uint64_t size, uint64_t flags);
+void kunmap_pages(void *addr, uint64_t size);
+
+typedef char link_symbol_ptr[];
+

include/neobbo.h

@@ -0,0 +1,20 @@
+#include <stdint.h>
+void kkill(void);
+
+typedef char link_symbol_ptr[];
+
+#define ALIGN_UP_MASK(x, mask)   (((x) + (mask)) & ~(mask))
+#define ALIGN_UP(x, val)         ALIGN_UP_MASK(x, (typeof(x))(val) - 1)
+
+#define ALIGN_DOWN_MASK(x, mask) ((x) & ~(mask))
+#define ALIGN_DOWN(x, val)       ALIGN_DOWN_MASK(x, (typeof(x))(val) - 1)
+
+#define IS_ALIGNED_MASK(x, mask) (((x) & (mask)) == 0)
+#define IS_ALIGNED(x, val)       IS_ALIGNED_MASK(x, (typeof(x))(val) - 1)
+
+#define PAGE_ROUND_UP(size)   ALIGN_UP(size, PAGE_SIZE)
+#define PAGE_ROUND_DOWN(size) ALIGN_DOWN(size, PAGE_SIZE)
+
+#define SIZE_IN_PAGES(size) size/PAGE_SIZE
+
+void *kmalloc(uint64_t size);

include/scheduler/sched.h

@@ -0,0 +1,33 @@
+#include <stdint.h>
+
+#pragma once
+
+typedef enum proc_state {
+    RUNNING = 3,
+    READY = 2,
+    SLEEPING = 1,
+    UNUSED = 0
+}proc_state;
+
+struct context {
+    uint64_t r15, r14, r13, r12, rbp, rbx, rip;
+};
+
+struct thread {
+    struct thread *next;
+    struct thread *prev;
+    uint64_t *mem;
+    uint64_t *kstack;
+    proc_state state;
+    uint16_t pid;
+    struct context *context;
+};
+
+void scheduler_init();
+[[noreturn]] void sched();
+void yield();
+
+#define PROC_MAX    512 // Max number of processes
+
+#define INITIAL_STACK_SIZE  0x10000
+

include/string.h

@@ -0,0 +1,16 @@
+#ifndef STRING_H
+#define STRING_H
+
+#include <stdint.h>
+
+void *memset(void *addr, int c, uint64_t n);
+
+void *memcpy(void *dest, void *src, uint64_t n);
+
+void *memmove(void *dest, const void *src, uint64_t n);
+
+int memcmp(const void *s1, const void *s2, uint64_t n);
+
+uint64_t strlen(const char* str);
+
+#endif

include/sys/acpi.h

@@ -0,0 +1,196 @@
+#include <stdint.h>
+#include <stdbool.h>
+typedef struct rsdp_t {
+    uint64_t signature;
+    uint8_t checksum;
+    uint8_t oemid[6];
+    uint8_t revision;
+    uint32_t rsdt_address;
+
+    uint32_t length;
+    uint64_t xsdt_address;
+    uint8_t ext_checksum;
+    uint8_t reserved[3];
+} __attribute((packed)) rsdp_t;
+
+typedef struct desc_header_t {
+    uint8_t signature[4];
+    uint32_t length;
+    uint8_t revision;
+    uint8_t checksum;
+    uint8_t oemid[6];
+    uint8_t oem_tableid[8];
+    uint32_t oem_revision;
+    uint32_t creator_id;
+    uint32_t creator_revision;
+} __attribute((packed)) desc_header_t;
+
+typedef struct rsdt_t {
+    desc_header_t header;
+    uint32_t entries_base[];
+} __attribute((packed)) rsdt_t;
+
+typedef struct xsdt_t {
+    desc_header_t header;
+    uint64_t entries_base[];
+} __attribute((packed)) xsdt_t;
+
+typedef struct ics_t {
+    uint8_t type;
+    uint8_t length;
+}__attribute((packed)) ics_t;
+
+typedef struct madt_t {
+    desc_header_t header;
+    uint32_t lic_address;
+    uint32_t flags;
+    ics_t ics[];
+} __attribute((packed)) madt_t;
+
+typedef struct lapic_ao_t {
+    ics_t ics;
+    uint16_t reserved;
+    uint64_t lapic_address;
+}__attribute((packed)) lapic_ao_t;
+
+typedef struct gas_t {
+    uint8_t address_space_id;
+    uint8_t reg_bit_width;
+    uint8_t reg_bit_offset;
+    uint8_t access_size;
+    uint64_t address;
+}__attribute((packed)) gas_t;
+
+typedef struct hpet_t {
+    desc_header_t header;
+    uint32_t event_timer_blkid;
+    gas_t base_address;
+    uint8_t hpet_number;
+    uint16_t minimum_clk_tick;
+    uint8_t oem_attribute;
+}__attribute((packed)) hpet_t;
+
+typedef struct ioapic_t{
+    ics_t ics;
+    uint8_t ioapic_id;
+    uint8_t reserved;
+    uint32_t ioapic_address;
+    uint32_t gsi_base;
+}__attribute((packed)) ioapic_t;
+
+typedef struct iso_t{
+    ics_t ics;
+    uint8_t bus;
+    uint8_t source;
+    uint32_t gsi;
+    uint16_t flags;
+}__attribute((packed)) iso_t;
+
+/* Copied from OSDEV wiki */
+typedef struct fadt_t{
+    desc_header_t header;
+    uint32_t FirmwareCtrl;
+    uint32_t Dsdt;
+
+    // field used in ACPI 1.0; no longer in use, for compatibility only
+    uint8_t  Reserved;
+
+    uint8_t  PreferredPowerManagementProfile;
+    uint16_t SCI_Interrupt;
+    uint32_t SMI_CommandPort;
+    uint8_t  AcpiEnable;
+    uint8_t  AcpiDisable;
+    uint8_t  S4BIOS_REQ;
+    uint8_t  PSTATE_Control;
+    uint32_t PM1aEventBlock;
+    uint32_t PM1bEventBlock;
+    uint32_t PM1aControlBlock;
+    uint32_t PM1bControlBlock;
+    uint32_t PM2ControlBlock;
+    uint32_t PMTimerBlock;
+    uint32_t GPE0Block;
+    uint32_t GPE1Block;
+    uint8_t  PM1EventLength;
+    uint8_t  PM1ControlLength;
+    uint8_t  PM2ControlLength;
+    uint8_t  PMTimerLength;
+    uint8_t  GPE0Length;
+    uint8_t  GPE1Length;
+    uint8_t  GPE1Base;
+    uint8_t  CStateControl;
+    uint16_t WorstC2Latency;
+    uint16_t WorstC3Latency;
+    uint16_t FlushSize;
+    uint16_t FlushStride;
+    uint8_t  DutyOffset;
+    uint8_t  DutyWidth;
+    uint8_t  DayAlarm;
+    uint8_t  MonthAlarm;
+    uint8_t  Century;
+
+    // reserved in ACPI 1.0; used since ACPI 2.0+
+    uint16_t BootArchitectureFlags;
+
+    uint8_t  Reserved2;
+    uint32_t Flags;
+
+    // 12 byte structure; see below for details
+    gas_t ResetReg;
+
+    uint8_t  ResetValue;
+    uint8_t  Reserved3[3];
+  
+    // 64bit pointers - Available on ACPI 2.0+
+    uint64_t                X_FirmwareControl;
+    uint64_t                X_Dsdt;
+
+    gas_t X_PM1aEventBlock;
+    gas_t X_PM1bEventBlock;
+    gas_t X_PM1aControlBlock;
+    gas_t X_PM1bControlBlock;
+    gas_t X_PM2ControlBlock;
+    gas_t X_PMTimerBlock;
+    gas_t X_GPE0Block;
+    gas_t X_GPE1Block;
+
+    gas_t sleep_ctrl_reg;
+    gas_t sleep_status_reg;
+
+    uint64_t hypervisor_vendor_id;
+    
+    uint8_t wbinvd;
+    uint8_t wbinvd_flush;
+
+    uint8_t proc_c1;
+    uint8_t p_lvl2_up;
+    uint8_t pwr_button;
+    uint8_t slp_button;
+    uint8_t fix_rtc;
+    uint8_t rtc_s4;
+    uint8_t tmr_val_ext;
+    uint8_t dck_cap;
+
+
+}__attribute((packed)) fadt_t;
+
+typedef struct conf_space_t {
+    uint64_t base_ecm;
+    uint16_t pci_seg_group;
+    uint8_t start_pci_num;
+    uint8_t end_pci_num;
+    uint32_t reserved;
+}__attribute((packed)) conf_space_t;
+
+typedef struct mcfg_t {
+    desc_header_t header;
+    uint64_t reserved;
+    conf_space_t conf_spaces[];
+}__attribute((packed)) mcfg_t;
+
+void acpi_init(void);
+uint64_t *find_acpi_table(char *signature);
+uint64_t *find_ics(uint64_t type);
+uint32_t find_iso(uint8_t legacy);
+
+
+

include/sys/pci.h

@@ -0,0 +1,102 @@
+#include <stdbool.h>
+#include <stdint.h>
+void pci_init();
+
+typedef struct pci_header_t {
+    uint16_t vendor_id;
+    uint16_t device_id;
+    uint16_t command;
+    uint16_t status;
+    uint8_t revision_id;
+    uint8_t prog_if;
+    uint8_t subclass;
+    uint8_t class_code;
+    uint8_t cache_line_size;
+    uint8_t latency_timer;
+    uint8_t header_type;
+    uint8_t bist;
+}__attribute((packed)) pci_header_t;
+
+typedef struct pci_header_0_t {
+    pci_header_t header;
+    uint32_t bar0;
+    uint32_t bar1;
+    uint32_t bar2;
+    uint32_t bar3;
+    uint32_t bar4;
+    uint32_t bar5;
+    uint32_t cardbus_cis_ptr;
+    uint16_t subsytem_vendor_id;
+    uint16_t subsystem_id;
+    uint32_t expansion_rom_base;
+    uint8_t capabilities_ptr;
+    uint8_t reserved1;
+    uint16_t reserved2;
+    uint32_t reserved3;
+    uint8_t interrupt_line;
+    uint8_t interrupt_pin;
+    uint8_t min_grant;
+    uint8_t max_latency;
+}__attribute((packed)) pci_header_0_t;
+
+typedef struct pci_header_1_t {
+    pci_header_t header;
+    uint32_t bar0;
+    uint32_t bar1;
+    uint8_t primary_bus_number;
+    uint8_t secondary_bus_number;
+    uint8_t subordinate_bus_number;
+    uint8_t secondary_latency_timer;
+    uint8_t io_base;
+    uint8_t io_limit;
+    uint16_t secondary_status;
+    uint16_t memory_base;
+    uint16_t memory_limit;
+    uint16_t prefetch_base_;
+    uint16_t prefetch_limit;
+    uint32_t prefetch_base_upper;
+    uint32_t prefetch_limit_upper;
+    uint16_t io_base_upper;
+    uint16_t io_limit_upper;
+    uint8_t capability_ptr;
+    uint8_t reserved1;
+    uint16_t reserved2;
+    uint32_t expansion_rom_base;
+    uint8_t interrupt_line;
+    uint8_t interrupt_pin;
+    uint16_t bridge_control;
+}__attribute((packed)) pci_header_1_t;
+
+typedef struct pci_header_ahci_t {
+    pci_header_t header;
+    uint32_t bar[4];
+    uint32_t ahci_bar;
+    uint16_t subsystem_id;
+    uint16_t subsytem_vendor_id;
+    uint32_t expansion_rom_base;
+    uint8_t capabilities_ptr;
+    uint16_t interrupt_info;
+    uint8_t min_grant;
+    uint8_t max_latency;
+
+}__attribute((packed)) pci_header_ahci_t;
+
+/* For internal use */
+typedef struct l84_pci_function_return {
+    bool multi; // If device has multiple functions this is set to 1, else set to 0. If set to 0, functions index 1-7 are ignored
+    uint64_t func_addr[8];
+} l84_pci_function_return;
+
+typedef struct pci_structure {
+    uint16_t segment;
+    uint8_t bus;
+    uint8_t device;
+    uint64_t func_addr[8];
+} pci_structure;
+
+l84_pci_function_return check_device(uint64_t bus, uint64_t device);
+
+uint64_t get_header(uint64_t bus, uint64_t device, uint64_t function);
+
+pci_header_t *pci_find_device(uint64_t class, int subclass);
+

include/sys/rand.h

@@ -0,0 +1,3 @@
+#include <stddef.h>
+void krand_init();
+size_t rand(void);